Q#1: Which register holds the address of the next instruction to be executed in the processor?
Answer: The Program Counter (PC) holds the address of the next instruction in memory that is to be executed.
Q#2: What do you understand by Machine Exception?
Answer: Anything that interrupts the normal flow of execution of instructions in the processor is called an exception. It may be generated by internal or external events such as divide by zero or an input device interrupt.
Q#3: How exception may be generated? Write the difference between external and internal exceptions.
Answer: Exceptions may be generated due to internal or external events during program execution.
- External Exceptions: These are asynchronous and generated by external devices like keyboard or mouse.
- Internal Exceptions: These are synchronous and occur due to instruction execution such as divide by zero.
Q#4: Write the structural RTL description for MOV instruction.
Answer: In MOV instruction, the data in register rb (source register) is moved to register ra (destination register). After instruction fetch, the contents of rb are transferred to buffer register C through the ALSU, and then from C to register ra through the internal uni-bus.
Q#5: Write the structural RTL description for Shift instruction.
Answer: Shift instructions require extra hardware to hold and decrement the shift count. If the ALSU performs only single-bit shifts, the data repeatedly passes through the ALSU until the count becomes zero. This problem can be solved using a barrel shifter, which performs multiple-bit shifts at once.
Q#6: Write one advantage and one disadvantage of Microprogramming.
Answer:
Advantage: Complex instruction sets can be implemented at a relatively low cost, and adding new instructions is easy.
Disadvantage: For simple machines, the additional hardware for control store and sequencer may become more complex than hardwired control.
Q#7: What is the difference between Memory Address Register (MAR) and Memory Buffer Register (MBR)?
Answer:
- MAR: Holds the address of the memory location that is to be accessed.
- MBR: Temporarily holds the data being transferred between memory and the processor.
Q#8: What is the NOP instruction and its significance in pipelining?
Answer: NOP (No Operation) is an instruction that tells the processor to perform no action during a clock cycle. It is used in pipelining to insert delays or bubbles to avoid hazards.
Q#9: What is the difference between Latency and Throughput?
Answer:
- Latency: Time required to process a single instruction.
- Throughput: Number of instructions processed per second.
Q#10: How many stages are in the pipelined version of SRC processor? Name them.
Answer: The SRC pipelined processor has five stages:
- Instruction Fetch
- Instruction Decode / Operand Fetch
- ALU Operation
- Memory Access
- Register Write
Q#11: What are the pipeline hazards?
Answer: Pipeline hazards are problems that prevent the next instruction from executing in the next clock cycle. There are three types:
- Branch Hazard
- Structural Hazard
- Data Hazard
Q#12: What is Pre-fetching?
Answer: Pre-fetching is a technique in which instructions are fetched in advance before they are needed for execution, which helps to reduce waiting time and increase processor speed.