Q#1: I/O systems in operating systems manage:
(A) Communication between CPU and peripheral devices
(B) Only CPU registers
(C) Main memory access
(D) Cache management
Answer: (A) Communication between CPU and peripheral devices
Q#2: I/O devices include:
(A) Disk drives, keyboards, mice, printers
(B) Only CPU registers
(C) Only main memory
(D) Only cache
Answer: (A) Disk drives, keyboards, mice, printers
Q#3: I/O devices can be classified as:
(A) Block devices and character devices
(B) CPU and memory
(C) Cache only
(D) Registers only
Answer: (A) Block devices and character devices
Q#4: Block devices:
(A) Transfer data in fixed-size blocks
(B) Transfer data character by character
(C) Only CPU registers
(D) Only cache
Answer: (A) Transfer data in fixed-size blocks
Q#5: Character devices:
(A) Transfer data one character at a time
(B) Transfer data in blocks
(C) Only CPU registers
(D) Only cache lines
Answer: (A) Transfer data one character at a time
Q#6: Device controllers:
(A) Interface between CPU and I/O devices
(B) CPU registers
(C) Cache memory
(D) Main memory
Answer: (A) Interface between CPU and I/O devices
Q#7: I/O ports are:
(A) Communication endpoints for devices
(B) Disk blocks
(C) CPU registers
(D) Cache lines
Answer: (A) Communication endpoints for devices
Q#8: Programmed I/O requires:
(A) CPU to issue I/O commands and wait for completion
(B) Only memory allocation
(C) Disk scheduling
(D) Cache access
Answer: (A) CPU to issue I/O commands and wait for completion
Q#9: Busy waiting occurs in:
(A) Programmed I/O
(B) Interrupt-driven I/O
(C) DMA
(D) Cache access
Answer: (A) Programmed I/O
Q#10: Interrupt-driven I/O avoids:
(A) Busy waiting
(B) Disk scheduling
(C) CPU idle
(D) Memory allocation
Answer: (A) Busy waiting
Q#11: Direct Memory Access (DMA) allows:
(A) Data transfer between memory and device without CPU involvement
(B) Only CPU access
(C) Only cache usage
(D) Disk transfer only
Answer: (A) Data transfer between memory and device without CPU involvement
Q#12: In DMA, CPU is interrupted:
(A) Only after entire block transfer
(B) For every byte
(C) Every clock cycle
(D) Never
Answer: (A) Only after entire block transfer
Q#13: Memory-mapped I/O maps:
(A) Device registers into memory address space
(B) Only CPU registers
(C) Disk sectors
(D) Cache lines
Answer: (A) Device registers into memory address space
Q#14: Isolated I/O uses:
(A) Separate address space for I/O devices
(B) Memory addresses
(C) Cache addresses
(D) CPU registers
Answer: (A) Separate address space for I/O devices
Q#15: I/O software includes:
(A) Device drivers and I/O control system
(B) CPU registers only
(C) Memory allocation
(D) Cache only
Answer: (A) Device drivers and I/O control system
Q#16: Device drivers provide:
(A) Abstraction between hardware and OS
(B) CPU registers
(C) Cache access
(D) Memory allocation
Answer: (A) Abstraction between hardware and OS
Q#17: I/O system software handles:
(A) Buffering, caching, and spooling
(B) Only CPU registers
(C) Only memory blocks
(D) Disk scheduling
Answer: (A) Buffering, caching, and spooling
Q#18: Buffering is used to:
(A) Temporarily store data between producer and consumer
(B) CPU idle
(C) Disk allocation
(D) Cache replacement
Answer: (A) Temporarily store data between producer and consumer
Q#19: Single buffering:
(A) Uses one buffer for data transfer
(B) Uses multiple buffers
(C) CPU idle
(D) Disk scheduling
Answer: (A) Uses one buffer for data transfer
Q#20: Double buffering:
(A) Uses two buffers to overlap I/O and CPU processing
(B) CPU idle
(C) Disk full
(D) Cache only
Answer: (A) Uses two buffers to overlap I/O and CPU processing
Q#21: Spooling stands for:
(A) Simultaneous Peripheral Operations On-Line
(B) Only disk scheduling
(C) CPU registers
(D) Memory allocation
Answer: (A) Simultaneous Peripheral Operations On-Line
Q#22: Spooling is commonly used for:
(A) Printing and batch processing
(B) Disk management only
(C) CPU scheduling only
(D) Cache only
Answer: (A) Printing and batch processing
Q#23: Interrupt vector contains:
(A) Addresses of interrupt service routines
(B) CPU registers
(C) Cache addresses
(D) Disk blocks
Answer: (A) Addresses of interrupt service routines
Q#24: Polling is:
(A) CPU periodically checks device status
(B) Device interrupts CPU
(C) DMA operation
(D) Memory-mapped I/O
Answer: (A) CPU periodically checks device status
Q#25: Advantages of interrupts over polling include:
(A) Efficient CPU utilization
(B) Higher CPU idle
(C) Disk scheduling
(D) Cache replacement
Answer: (A) Efficient CPU utilization
Q#26: Block-oriented devices include:
(A) Disks
(B) Keyboard
(C) Mouse
(D) Printer
Answer: (A) Disks
Q#27: Character-oriented devices include:
(A) Keyboard, mouse, serial ports
(B) Disk only
(C) SSD only
(D) Tape only
Answer: (A) Keyboard, mouse, serial ports
Q#28: Logical I/O addresses are mapped to:
(A) Physical device addresses
(B) CPU registers
(C) Cache only
(D) Memory blocks
Answer: (A) Physical device addresses
Q#29: Asynchronous I/O allows:
(A) CPU and I/O operations to proceed concurrently
(B) CPU to wait
(C) Only memory access
(D) Only cache usage
Answer: (A) CPU and I/O operations to proceed concurrently
Q#30: Synchronous I/O requires:
(A) CPU waits until I/O completes
(B) CPU and I/O concurrent
(C) Only disk scheduling
(D) Cache management
Answer: (A) CPU waits until I/O completes
Q#31: I/O scheduling improves:
(A) Throughput and response time of devices
(B) Only CPU speed
(C) Only memory access
(D) Cache usage
Answer: (A) Throughput and response time of devices
Q#32: Common disk scheduling algorithms include:
(A) FCFS, SSTF, SCAN, C-SCAN
(B) FIFO only
(C) CPU registers
(D) Cache only
Answer: (A) FCFS, SSTF, SCAN, C-SCAN
Q#33: I/O system can use:
(A) Polling, interrupts, DMA
(B) CPU registers only
(C) Cache only
(D) Memory only
Answer: (A) Polling, interrupts, DMA
Q#34: Device status register indicates:
(A) Device condition and readiness
(B) CPU idle
(C) Disk full
(D) Cache status
Answer: (A) Device condition and readiness
Q#35: Command register stores:
(A) Commands sent to device
(B) CPU instruction
(C) Cache command
(D) Memory block
Answer: (A) Commands sent to device
Q#36: Data register holds:
(A) Data to/from device
(B) CPU register
(C) Cache line
(D) Disk block
Answer: (A) Data to/from device
Q#37: I/O multiplexing allows:
(A) Multiple I/O operations simultaneously
(B) Single operation only
(C) Only CPU tasks
(D) Only memory tasks
Answer: (A) Multiple I/O operations simultaneously
Q#38: I/O buffering improves:
(A) Performance by decoupling CPU and device speed
(B) CPU idle only
(C) Disk scheduling only
(D) Cache management only
Answer: (A) Performance by decoupling CPU and device speed
Q#39: Device independence allows:
(A) OS to access devices without knowing hardware details
(B) Only CPU usage
(C) Only memory allocation
(D) Only cache management
Answer: (A) OS to access devices without knowing hardware details
Q#40: Logical device driver provides:
(A) Uniform interface for I/O operations
(B) CPU register management
(C) Memory allocation
(D) Cache replacement
Answer: (A) Uniform interface for I/O operations
Q#41: Physical device driver handles:
(A) Device-specific operations
(B) CPU only
(C) Memory only
(D) Cache only
Answer: (A) Device-specific operations
Q#42: I/O request packet contains:
(A) Device number, operation, buffer, size
(B) CPU register info
(C) Cache address
(D) Memory block info
Answer: (A) Device number, operation, buffer, size
Q#43: Spooling is a form of:
(A) Indirect I/O
(B) Direct I/O
(C) CPU-only process
(D) Memory-only process
Answer: (A) Indirect I/O
Q#44: Interrupt-driven I/O improves:
(A) CPU efficiency
(B) Disk access
(C) Cache performance
(D) Memory management
Answer: (A) CPU efficiency
Q#45: DMA controller manages:
(A) Direct data transfer between memory and device
(B) Only CPU
(C) Only cache
(D) Disk scheduling
Answer: (A) Direct data transfer between memory and device
Q#46: I/O performance depends on:
(A) Device speed, CPU speed, OS efficiency
(B) Only CPU
(C) Only memory
(D) Cache only
Answer: (A) Device speed, CPU speed, OS efficiency
Q#47: I/O bottleneck occurs when:
(A) Device speed is slower than CPU or memory
(B) CPU idle
(C) Memory full
(D) Cache miss
Answer: (A) Device speed is slower than CPU or memory
Q#48: Asynchronous devices signal:
(A) CPU when ready or complete operation
(B) CPU continuously
(C) Only memory
(D) Cache only
Answer: (A) CPU when ready or complete operation
Q#49: Synchronous devices require:
(A) CPU waits for operation to complete
(B) CPU continues
(C) Only disk scheduling
(D) Only cache
Answer: (A) CPU waits for operation to complete
Q#50: Main goal of I/O system:
(A) Efficient, reliable, and safe data transfer between CPU and devices
(B) CPU optimization only
(C) Cache management only
(D) Memory allocation only
Answer: (A) Efficient, reliable, and safe data transfer between CPU and devices