MCQs

Q#1: What is the instruction length of the SRC processor?
(A) 8 bits
(B) 16 bits
(C) 32 bits
(D) 64 bits
Answer: (C) 32 bits

Q#2: Which one of the following is the memory organization of FALCON-E processor?
(A) 2⁸ × 8 bits
(B) 2¹⁶ × 8 bits
(C) 2³² × 8 bits
(D) 2⁶⁴ × 8 bits
Answer: (B) 2¹⁶ × 8 bits

Q#3: “If P = 1, then load the contents of register R1 into register R2”. This statement in RTL is written as:
(A) R1 ← R2
(B) P: R1 ← R2
(C) P: R2 ← R1
(D) P: R2 ← R1, P: R1 ← R2
Answer: (C) P: R2 ← R1

Q#4: The instruction ______ will load register R3 with the contents of memory location M[PC+56].
(A) Add R3, 56
(B) lar R3, 56
(C) ldr R3, 56
(D) str R3, 56
Answer: (C) ldr R3, 56

Q#5: ______ are faster than cache memory.
(A) Accumulator register
(B) CPU registers
(C) I/O devices
(D) ROM
Answer: (B) CPU registers

Q#6: If two RTL operations occur simultaneously, which symbol is used to separate them?
(A) Arrow (←)
(B) Colon (:)
(C) Comma (,)
(D) Parentheses ( )
Answer: (C) Comma (,)

Q#7: Prefetching can be considered a primitive form of ______.
(A) Pipelining
(B) Multiprocessing
(C) Self-execution
(D) Exception
Answer: (A) Pipelining

Q#8: The processor must save its state so it can be restored upon return from the ______.
(A) Exception
(B) Function
(C) Stack
(D) Thread
Answer: (A) Exception

Q#9: Which circuit design level is called the gate level?
(A) Logic Design Level
(B) Circuit Level
(C) Mask Level
(D) None of the given
Answer: (A) Logic Design Level

Q#10: ______ enables input to the PC to receive a value currently on the internal processor bus.
(A) LPC
(B) INC4
(C) LC
(D) Cout
Answer: (A) LPC

Q#11: ______ operation is required to change the processor’s state to a known defined value.
(A) Change
(B) Reset
(C) Update
(D) None of the given
Answer: (B) Reset

Q#12: There are ______ types of reset operations in SRC.
(A) Two
(B) Three
(C) Four
(D) Five
Answer: (A) Two

Q#13: ______ controller controls the sequence of the flow of microinstructions.
(A) Multiplexer
(B) Microprogram
(C) ALU
(D) None of the given
Answer: (B) Microprogram

Q#14: FALCON-A processor bus has 16 lines (16-bit) while SRC bus is ______ wide.
(A) 8 bits
(B) 24 bits
(C) 32 bits
(D) 64 bits
Answer: (C) 32 bits

Q#15: Which statements are correct about RISC architecture?
(i) Instruction set is small
(ii) Arithmetic/logic instructions cannot access memory directly
(iii) Large number of registers available
(iv) Instructions easily decoded using hardwired control

(A) (i) and (iii) only
(B) (i), (iii) and (iv)
(C) (i), (ii) and (iii) only
(D) (i), (ii), (iii) and (iv)
Answer: (D) (i), (ii), (iii) and (iv)

Q#16: Which register holds the instruction that is currently being executed?
(A) Accumulator
(B) Address Mask
(C) Instruction Register
(D) Program Counter
Answer: (C) Instruction Register

Short Questions

Q#17: Write the RTL statement for the arithmetic instruction.
Answer:
If opcode is 0, the instruction is ADD. The values of registers rb and rc are added and stored in ra.
RTL representation:
ra ← rb + rc

Q#18: Write the SRC instruction fields using RTL.
Answer:
Operation code field → op<4..0> ← IR<31..27>
Target register field → ra<4..0> ← IR<26..22>
Operand/address index → rb<4..0> ← IR<21..17>
Second operand/shift count → rc<4..0> ← IR<16..12>

Q#19: How can you define microprogram?
Answer:
A microprogram is a sequence of microinstructions stored in control memory that generates control signals to execute machine instructions.

Q#20: What is the role of timing step generator in a processor?
Answer:
The timing step generator produces sequential timing signals that control the execution steps of instructions and ensure operations occur in the correct order.

Q#21: What is the utility of reset operation and when is it required?
Answer:
Reset operation initializes the processor to a known state. It clears the control step counter and loads the program counter with a predefined value. It is required when the system starts or when an error occurs.

Q#22: Write the structural RTL description for unconditional jump instruction (jump [ra + c2]).
Answer:

T0–T2: Instruction fetch
T3: C ← ra + c2
T4: PC ← C

Q#23: What function is performed by reset operation? What are its types?
Answer:
The reset operation initializes the processor state and reloads the program counter.

Types of reset operations:
• Hard Reset – Initializes PC and all registers.
• Soft Reset – Initializes only the program counter.