Q#1: What is the instruction length of the FALCON-A processor?
(A) 8 bits
(B) 16 bits
(C) 32 bits
(D) 64 bits
Answer: (B) 16 bits
Q#2: What is the instruction length of the SRC processor?
(A) 8 bits
(B) 16 bits
(C) 32 bits
(D) 64 bits
Answer: (C) 32 bits
Q#3: What does the word “D” in the D-Flip-Flop stand for?
(A) Double
(B) Data
(C) Digital
(D) Dynamic
Answer: (B) Data
Q#4: “If P = 1, then load the contents of register R1 into register R2”. This statement in RTL is written as:
(A) R1 ← R2
(B) P: R1 ← R2
(C) P: R2 ← R1
(D) P: R2 ← R1, P: R1 ← R2
Answer: (C) P: R2 ← R1
Q#5: Almost every commercial computer has its own particular ______ language.
(A) Assembly language
(B) English language
(C) Higher level language
(D) 3GL
Answer: (A) Assembly language
Q#6: A ______ is a computer program used to test and debug other programs.
(A) Linker
(B) Loader
(C) Debugger
(D) Compiler
Answer: (C) Debugger
Q#7: What is the working of Processor Status Word (PSW)?
(A) To hold the current status of the processor
(B) To hold the address of the current process
(C) To hold the instruction currently executing
(D) To hold the address of the next instruction
Answer: (A) To hold the current status of the processor
Q#8: The instruction ______ loads register R3 with the contents of memory location M[PC+56].
(A) Add R3, 56
(B) lar R3, 56
(C) ldr R3, 56
(D) str R3, 56
Answer: (C) ldr R3, 56
Q#9: Motorola MC68000 is an example of ______ microprocessor.
(A) CISC
(B) RISC
(C) SRC
(D) FALCON
Answer: (A) CISC
Q#10: Which control signal allows the contents of Program Counter to be written onto the internal processor bus?
(A) INC4
(B) LPC
(C) PCout
(D) LC
Answer: (C) PCout
Q#11: Op<4..0> := IR<15..11> represents the ______ of FALCON-A instruction.
(A) Operation code field
(B) Target register field
(C) Operand or address index
(D) Second operand
Answer: (A) Operation code field
Q#12: ______ operation is required to change the processor’s state to a known defined value.
(A) Change
(B) Reset
(C) Update
(D) Halt
Answer: (B) Reset
Q#13: ______ is defined as the number of instructions processed per second.
(A) Throughput
(B) Latency
(C) Hazards
(D) Throughput and Latency
Answer: (A) Throughput
Q#14: Which registers are programmer invisible and hold operand or result values while the bus is busy?
(A) Instruction Register
(B) Memory Address Register
(C) Memory Buffer Register
(D) Registers A and C
Answer: (D) Registers A and C
Q#15: Anything that interrupts the normal flow of execution of instructions in the processor is called a/an ______.
(A) Function
(B) Exception
(C) Assembler
(D) Machine
Answer: (B) Exception
Q#16: In pipelining, ______ is increased by overlapping instruction execution.
(A) Latency
(B) Throughput
(C) Execution time
(D) Clock speed
Answer: (B) Throughput
Q#17: Which control signal enables input to the PC to receive a value from the internal processor bus?
(A) LPC
(B) INC4
(C) LC
(D) Cout
Answer: (A) LPC
Q#18: In which addressing mode is the data part of the instruction itself?
(A) Direct addressing
(B) Immediate addressing
(C) Indirect addressing
(D) Register addressing
Answer: (B) Immediate addressing
Q#19: Which hazard occurs when attempting to access the same resource in different ways at the same time?
(A) RAW data hazard
(B) Structural hazard
(C) Branch hazard
(D) Complex hazard
Answer: (B) Structural hazard
Q#20: ______ is the arithmetic portion of the Von Neumann architecture consisting of registers, buses, arithmetic units and shifters.
(A) Virtual Memory
(B) Data Path
(C) Structural RTL
(D) Timing
Answer: (B) Data Path
Q#21: Which type of instructions load data from memory into registers or store data from registers into memory?
(A) Arithmetic
(B) Control
(C) Data transfer
(D) Floating point
Answer: (C) Data transfer
Q#22: What functionality is performed by the instruction “lar R3, 36” of SRC?
(A) Loads R3 with contents of M[PC+36]
(B) Loads R3 with the relative address PC+36
(C) Stores R3 into M[PC+36]
(D) No operation
Answer: (B) Loads R3 with the relative address PC+36