Q#1: FALCON-A processor bus has 16 lines or is 16-bits wide while that of SRC is ___ wide.
(A) 8-bits
(B) 16-bits
(C) 32-bits
(D) 64-bits
Answer: (C) 32-bits
Q#2: Which one of the following is a bi-stable device capable of storing one bit of information?
(A) Decoder
(B) Flip-Flop
(C) Multiplexer
(D) Diplexer
Answer: (B) Flip-Flop
Q#3: Which instruction is used to store register to memory using relative address?
(A) ld instruction
(B) ldr instruction
(C) lar instruction
(D) str instruction
Answer: (D) str instruction
Q#4: Which instruction will load register R3 with the contents of memory location M[PC+56]?
(A) Add R3, 56
(B) lar R3, 56
(C) ldr R3, 56
(D) str R3, 56
Answer: (C) ldr R3, 56
Q#5: ___ operation occurs when the processor starts in a new defined value/state.
(A) Change
(B) Reset
(C) Update
(D) None of the given
Answer: (B) Reset
Q#6: Which type of instructions help in changing the flow of the program when required?
(A) Arithmetic
(B) Control
(C) Data transfer
(D) Floating point
Answer: (B) Control
Q#7: Which register holds the address of the next instruction to be executed?
(A) Accumulator
(B) Address Mask
(C) Instruction Register
(D) Program Counter
Answer: (D) Program Counter
Q#8: The external interface of FALCON-A consists of a ___ address bus and ___ data bus.
(A) 8-bit, 8-bit
(B) 16-bit, 16-bit
(C) 16-bit, 24-bit
(D) 16-bit, 32-bit
Answer: (B) 16-bit, 16-bit
Q#9: What is the instruction length of the SRC processor?
(A) 8 bits
(B) 16 bits
(C) 32 bits
(D) 64 bits
Answer: (C) 32 bits
Q#10: In RTL, if two operations occur simultaneously, which symbol is used to separate them?
(A) Arrow ¬
(B) Colon :
(C) Comma ,
(D) Parentheses ()
Answer: (C) Comma ,
Q#11: The processor must save its context so that it can be restored upon return from an ___.
(A) Exception
(B) Function
(C) Stack
(D) Thread
Answer: (A) Exception
Q#12: Which register holds the instruction that is currently being executed?
(A) Accumulator
(B) Address Mask
(C) Instruction Register
(D) Program Counter
Answer: (C) Instruction Register
Q#13: The code size of a 2-address instruction is:
(A) 5 bytes
(B) 7 bytes
(C) 3 bytes
(D) 2 bytes
Answer: (B) 7 bytes
Q#14: An assembler that runs on one processor and translates assembly code for another processor is called a:
(A) Compiler
(B) Cross assembler
(C) Debugger
(D) Linker
Answer: (B) Cross assembler
Q#15: What functionality is performed by the instruction “lar R3, 36” of SRC?
(A) Loads R3 with contents of M[PC+36]
(B) Loads R3 with the relative address (PC+36)
(C) Stores R3 contents into M[PC+36]
(D) No operation
Answer: (B) Loads R3 with the relative address (PC+36)
Q#16: Which operator is used to name registers in Register Transfer Language (RTL)?
(A) :=
(B) &
(C) %
(D) ©
Answer: (A) :=
Q#17: Which instructions move data between registers and memory?
(A) Arithmetic/Logic
(B) Load/Store
(C) Test/Branch
(D) None of the given
Answer: (B) Load/Store
Q#18: What does the instruction “ldr R3, 58” of SRC do?
(A) Loads R3 with contents of M[PC+58]
(B) Loads R3 with relative address PC+58
(C) Stores R3 into M[PC+58]
(D) No operation
Answer: (A) Loads R3 with contents of M[PC+58]
Q#19: Type-A SRC instruction format includes:
(A) 3 ALU registers
(B) 4 ALU registers
(C) 1 ALU register
(D) 2 ALU registers
Answer: (D) 2 ALU registers