Q#1: Main memory is also called:
(A) Primary memory
(B) Secondary memory
(C) Cache memory
(D) Virtual memory
Answer: (A) Primary memory
Q#2: Main memory is:
(A) Volatile memory used to store data and instructions
(B) Non-volatile storage
(C) Permanent disk storage
(D) External storage
Answer: (A) Volatile memory used to store data and instructions
Q#3: RAM stands for:
(A) Random Access Memory
(B) Read Access Memory
(C) Read Only Memory
(D) Run Access Memory
Answer: (A) Random Access Memory
Q#4: Types of RAM include:
(A) Static RAM (SRAM) and Dynamic RAM (DRAM)
(B) Only ROM
(C) Only Cache
(D) Only Flash
Answer: (A) Static RAM (SRAM) and Dynamic RAM (DRAM)
Q#5: ROM stands for:
(A) Read-Only Memory
(B) Random-Only Memory
(C) Run-Only Memory
(D) Register-Only Memory
Answer: (A) Read-Only Memory
Q#6: ROM is:
(A) Non-volatile memory
(B) Volatile memory
(C) Temporary storage
(D) CPU register
Answer: (A) Non-volatile memory
Q#7: Memory hierarchy is organized based on:
(A) Speed, cost, and size
(B) Only speed
(C) Only cost
(D) Only size
Answer: (A) Speed, cost, and size
Q#8: Cache memory is:
(A) Fast memory between CPU and main memory
(B) Slow disk memory
(C) Only secondary storage
(D) Only registers
Answer: (A) Fast memory between CPU and main memory
Q#9: Main memory stores:
(A) Both data and instructions for the CPU
(B) Only data
(C) Only instructions
(D) Only disk blocks
Answer: (A) Both data and instructions for the CPU
Q#10: Volatile memory loses content:
(A) When power is turned off
(B) Permanently
(C) Never
(D) Only in CPU reset
Answer: (A) When power is turned off
Q#11: Static RAM (SRAM) uses:
(A) Flip-flops to store data
(B) Capacitors
(C) Disks
(D) Only registers
Answer: (A) Flip-flops to store data
Q#12: Dynamic RAM (DRAM) uses:
(A) Capacitors and requires periodic refresh
(B) Flip-flops
(C) Disks
(D) Only registers
Answer: (A) Capacitors and requires periodic refresh
Q#13: Memory word size refers to:
(A) Number of bits accessed at a time
(B) Only address lines
(C) CPU speed
(D) Disk sector size
Answer: (A) Number of bits accessed at a time
Q#14: Memory access time is:
(A) Time to read/write data from/to memory
(B) Time to process instruction
(C) Time to access disk
(D) Time to allocate CPU
Answer: (A) Time to read/write data from/to memory
Q#15: Memory address is:
(A) Unique location identifier for each memory word
(B) CPU register
(C) Disk block number
(D) Only cache line
Answer: (A) Unique location identifier for each memory word
Q#16: Contiguous memory allocation:
(A) Allocates consecutive memory blocks to a process
(B) Non-contiguous allocation
(C) Only disk allocation
(D) Only CPU allocation
Answer: (A) Allocates consecutive memory blocks to a process
Q#17: Fragmentation occurs in memory when:
(A) Free memory is broken into small blocks
(B) Memory is continuous
(C) Disk fails
(D) CPU idle
Answer: (A) Free memory is broken into small blocks
Q#18: Internal fragmentation is:
(A) Wasted memory inside allocated block
(B) Wasted memory outside block
(C) CPU idle
(D) Disk failure
Answer: (A) Wasted memory inside allocated block
Q#19: External fragmentation is:
(A) Wasted memory outside allocated blocks
(B) Wasted memory inside blocks
(C) CPU idle
(D) Disk failure
Answer: (A) Wasted memory outside allocated blocks
Q#20: Paging solves:
(A) External fragmentation
(B) Internal fragmentation
(C) CPU idle
(D) Disk full
Answer: (A) External fragmentation
Q#21: Page table stores:
(A) Mapping of logical to physical addresses
(B) CPU registers
(C) Disk addresses
(D) Cache memory
Answer: (A) Mapping of logical to physical addresses
Q#22: Each process has:
(A) Its own page table
(B) Shared page table
(C) Only CPU registers
(D) Only disk block
Answer: (A) Its own page table
Q#23: Segmentation divides memory based on:
(A) Logical units like code, data, stack
(B) Fixed size pages
(C) Only CPU registers
(D) Disk sectors
Answer: (A) Logical units like code, data, stack
Q#24: Memory protection is done using:
(A) Base and limit registers
(B) Only CPU scheduling
(C) Only cache
(D) Disk controller
Answer: (A) Base and limit registers
Q#25: Relocation of memory allows:
(A) Processes to be moved in memory without changing logical addresses
(B) Only CPU relocation
(C) Only disk relocation
(D) Only register relocation
Answer: (A) Processes to be moved in memory without changing logical addresses
Q#26: Swapping moves:
(A) Entire process between main memory and secondary storage
(B) Only CPU register
(C) Only disk block
(D) Only cache line
Answer: (A) Entire process between main memory and secondary storage
Q#27: Memory compaction:
(A) Combines free memory holes to reduce external fragmentation
(B) Divides memory
(C) Only CPU scheduling
(D) Only disk allocation
Answer: (A) Combines free memory holes to reduce external fragmentation
Q#28: Virtual memory allows:
(A) Processes to execute without loading entirely in main memory
(B) Only CPU idle
(C) Only cache usage
(D) Only disk management
Answer: (A) Processes to execute without loading entirely in main memory
Q#29: Demand paging loads:
(A) Only required pages into memory
(B) Entire process
(C) Only CPU registers
(D) Only cache lines
Answer: (A) Only required pages into memory
Q#30: Page fault occurs when:
(A) Required page is not in main memory
(B) CPU idle
(C) Disk failure
(D) Cache miss
Answer: (A) Required page is not in main memory
Q#31: Memory hierarchy levels include:
(A) Registers, cache, main memory, secondary memory
(B) Only main memory
(C) Only CPU
(D) Only disk
Answer: (A) Registers, cache, main memory, secondary memory
Q#32: Memory access time decreases as we move:
(A) From main memory to registers
(B) From registers to disk
(C) From disk to memory
(D) Only cache to disk
Answer: (A) From main memory to registers
Q#33: Memory interleaving improves:
(A) Memory bandwidth by accessing multiple modules in parallel
(B) Only CPU utilization
(C) Only disk allocation
(D) Only cache efficiency
Answer: (A) Memory bandwidth by accessing multiple modules in parallel
Q#34: Physical address refers to:
(A) Actual location in main memory
(B) Logical address
(C) Disk address
(D) Cache line
Answer: (A) Actual location in main memory
Q#35: Logical address refers to:
(A) Address generated by CPU
(B) Physical memory location
(C) Disk address
(D) Cache line
Answer: (A) Address generated by CPU
Q#36: Base register stores:
(A) Starting physical address of process in memory
(B) CPU register value
(C) Disk block
(D) Cache line
Answer: (A) Starting physical address of process in memory
Q#37: Limit register stores:
(A) Size of the process in memory
(B) CPU register
(C) Disk block size
(D) Cache size
Answer: (A) Size of the process in memory
Q#38: Contiguous allocation suffers from:
(A) External fragmentation
(B) Internal fragmentation
(C) CPU idle
(D) Disk failure
Answer: (A) External fragmentation
Q#39: Paging suffers from:
(A) Internal fragmentation
(B) External fragmentation
(C) CPU idle
(D) Disk full
Answer: (A) Internal fragmentation
Q#40: Segmentation provides:
(A) User view of memory
(B) Only CPU scheduling
(C) Only disk allocation
(D) Only cache management
Answer: (A) User view of memory
Q#41: Translation Lookaside Buffer (TLB) is:
(A) Cache for page table entries
(B) Disk cache
(C) CPU register
(D) Memory block
Answer: (A) Cache for page table entries
Q#42: TLB improves:
(A) Virtual memory access speed
(B) Only CPU scheduling
(C) Only disk speed
(D) Only cache speed
Answer: (A) Virtual memory access speed
Q#43: Main memory size is measured in:
(A) Bytes, KB, MB, GB
(B) Seconds
(C) CPU cycles
(D) Disk blocks
Answer: (A) Bytes, KB, MB, GB
Q#44: Memory word is:
(A) Fixed number of bits handled as a unit
(B) CPU register
(C) Disk block
(D) Cache line
Answer: (A) Fixed number of bits handled as a unit
Q#45: Memory modules are:
(A) Physical units of main memory
(B) CPU units
(C) Disk sectors
(D) Cache lines
Answer: (A) Physical units of main memory
Q#46: DRAM requires:
(A) Periodic refresh
(B) No refresh
(C) Only CPU scheduling
(D) Only disk allocation
Answer: (A) Periodic refresh
Q#47: SRAM is faster than DRAM because:
(A) Does not require refresh
(B) Requires refresh
(C) Only CPU-bound
(D) Only memory-bound
Answer: (A) Does not require refresh
Q#48: Memory interleaving divides memory into:
(A) Multiple modules accessed in parallel
(B) Single module
(C) CPU registers
(D) Disk sectors
Answer: (A) Multiple modules accessed in parallel
Q#49: Main memory acts as:
(A) Interface between CPU and secondary storage
(B) Only CPU register
(C) Only disk cache
(D) Only network buffer
Answer: (A) Interface between CPU and secondary storage
Q#50: Goal of main memory management:
(A) Efficient and safe allocation to processes
(B) Only CPU optimization
(C) Only disk usage
(D) Only cache management
Answer: (A) Efficient and safe allocation to processes