1. . Shift left register shifts data from?
(A) Left to right
(B) Right to left
(C) Up to down
(D) Down to up
2. . A shift register has characteristics:
(A) Memory
(B) Shift only
(C) Both memory and shift
(D) None of these
3. . A stage in a shift register consists of:
(A) A Latch
(B) A flip flop
(C) A byte of storage
(D) 4 bits of storage
4. . Shift register is constructed by combining:
(A) Diodes
(B) Transistors
(C) Flip Flops
(D) SCRs
5. . 4-bit register consists of number of flip flops:
(A) 8
(B) 6
(C) 4
(D) 16
6. . The inter data into the register is called:
(A) Loading data
(B) Storing data
(C) Writing data
(D) All of these
7. . A shift register can accept data bits in:
(A) Serial fashion
(B) Parallel fashion
(C) Both a and b
(D) None of these
8. . SISO data shifting process is:
(A) Slow
(B) Fast
(C) Very fast
(D) None of these
9. . To serially shift a byte of data into shift register, there must be:
(A) One clock pulse
(B) One load pulse
(C) Eight clock pulses
(D) One clock pulse for each 1 in the data
10. . How many clock pulses will be required to completely load serially a 5-bit shift register?
(A) 2
(B) 3
(C) 4
(D) 5
11. . Data load to each flip flop separately:
(A) SISO
(B) PISO
(C) PIPO
(D) “b” and “c”
12. . It is used for the temporary storage of data or time delay device:
(A) PIPO
(B) PISO
(C) SISO
(D) SIPO
13. . The full form of SIPO is ___________:
(A) Parallel-in Serial-out
(B) Serial-in Serial-out
(C) Serial-In Peripheral-Out
(D) Serial-in Parallel-out
14. . Based on how binary information is entered or shifted out, shift registers are classified into _______ categories:
(A) 2
(B) 3
(C) 4
(D) 5
15. . The register is a type of ___________:
(A) Sequential circuit
(B) Combinational circuit
(C) CPU
(D) LATCHES
16. . Registers capable of shifting in one direction is ___________:
(A) Universal shift register
(B) Unidirectional shift register
(C) Uni polar shift register
(D) Unique shift register
17. . A register that is used to store binary information is called ___________:
(A) Binary register
(B) Shift register
(C) D – Register
(D) Data register
18. . In serial shifting method, data shifting occurs ____________:
(A) One bit at a time
(B) Simultaneously
(C) Two bit at a time
(D) Four bit at a time
19. . In a parallel in/parallel out shift register, D0 = 1, D1 = 1, D2 = 1, and D3 = 0. After one clock pulse, the data outputs are ________:
(A) 1110
(B) 0001
(C) 1100
(D) 1000
20. . What type of register would have a complete binary number shifted in one bit at a time and have all the stored bits shifted out one at a time?
(A) SIPO
(B) SISO
(C) PIPO
(D) PISO