1. . A sequential circuit consists of:
(A) Combinational circuit
(B) Memory element
(C) Feedback
(D) All of these
2. . A digital element which can store one bit of binary data at a time:
(A) Multiplexer
(B) Flip Flop
(C) Encoder
(D) Clock
3. . Flip flop has stable state:
(A) 2
(B) 1
(C) 3
(D) 4
4. . Flip flop basically a:
(A) Counting Element
(B) Memory Element
(C) Timing Element
(D) None of these
5. . Basic building blocks of combinational circuits are:
(A) Flip Flops
(B) Logic Gates
(C) Timers
(D) Registers
6. . Flip flops are related to the circuits:
(A) Combinational
(B) Sequential
(C) Both a & b
(D) None of these
7. . It is the simplest type of flip flop:
(A) RS flip flop
(B) D flip flop
(C) JK flip flop
(D) T flip flop
8. . RS flip flop has:
(A) Two inputs & two outputs
(B) Two inputs & one output
(C) Three inputs & Two outputs
(D) None of these
9. . A basic RS latch consists of this gate:
(A) NAND Gate
(B) NOR Gate
(C) a or b
(D) OR Gate
10. . Clocked RS flip flop has:
(A) Two inputs & two outputs
(B) Two inputs & one output
(C) Three inputs & Two outputs
(D) None of these
11. . The number of Data input of D – flip flop is:
(A) 1
(B) 2
(C) 3
(D) 4
12. . This condition is not happened in D - Flip flop:
(A) Set
(B) Reset
(C) Race
(D) None of these
13. . When a digital circuit triggers on the transition of clock pulse, it is called:
(A) Level triggering
(B) Edge triggering
(C) Clearing
(D) Loading
14. . When a digital circuit triggers on the level of clock pulse, it is called:
(A) Level triggering
(B) Edge triggering
(C) Clearing
(D) Loading
15. . It is used to trigger flip flop on pulse transition:
(A) Resistive Coupling
(B) Inductive Coupling
(C) Capacitive Coupling
(D) All of these
16. . JK flip flop has:
(A) Two inputs & two outputs
(B) Two inputs & one output
(C) Three inputs & Two outputs
(D) None of these
17. . This flip flop is called universal flip flop:
(A) RS Flip flop
(B) D flip flop
(C) Clocked RS flip flop
(D) JK flip flop
18. . Toggle means:
(A) Set
(B) Reset
(C) Change to opposite state
(D) No change
19. . When both inputs of JK flip flop are HIGH (1), then it is in state:
(A) Set
(B) Reset
(C) Toggle
(D) No change
20. . When both inputs of JK flip flop are LOW (0), then it is in state:
(A) Set
(B) Reset
(C) Toggle
(D) No change
21. . A flip flop can store only:
(A) 1 bit
(B) 8 bits
(C) 16 bits
(D) 2 bits
22. . Provide clock pulse to any digital circuit is called:
(A) Enabling
(B) Triggering
(C) Clocking
(D) Energizing
23. . T flip flop can be implemented by using this flip flop:
(A) RS flip flop
(B) Clocked RS flip flop
(C) JK flip flop
(D) All of these
24. . JK flip flop is a circuit:
(A) Single feedback
(B) Double feedback
(C) Without feedback
(D) None of these