1. . When the input to an inverter is LOW (0), the output is
(A) HIGH or 0
(B) LOW or 0
(C) HIGH or 1
(D) LOW or 1
2. . An inverter performs an operation known as
(A) complementation
(B) Assertion
(C) Inversion
(D) both a and c
3. . Logical expression for NOT gate is:
(A) A=0
(B) A=1
(C) A=A
(D) A=A’
4. . Logical expression for AND gate is:
(A) X=A+B
(B) X=A.B
(C) X=AB
(D) None of these
5. . The output of an OR gate with inputs A, B and C is 0 (LOW) when
(A) A = 0, B = 0, C = 0
(B) A = 0, B = 1, C = 1
(C) both a and b
(D) None
6. . Logical expression for OR gate is:
(A) X=A+B
(B) X=A.B
(C) X=AB
(D) None of these
7. . A pulse is applied to each input of a 2-input NAND gate. One pulse goes HIGH at t = 0 and goes back LOW at t = 1 ms. The other pulse goes HIGH at t = 0.8 ms and goes back LOW at t = 3 ms. The output pulse can be described as follows:
(A) It goes LOW at t = 0 and back HIGH at t = 3 ms.
(B) It goes LOW at t = 0.8 ms and back HIGH at t = 3 ms.
(C) It goes LOW at t = 0.8 ms and back HIGH at t = 1 ms.
(D) It goes LOW at t = 0.8 ms and back LOW at t = 1 ms.
8. . A pulse is applied to each input of a 2-input NOR gate. The other pulse goes HIGH at t = 0.8 ms and goes back LOW at t = 3 ms. The output pulse can be described as follows:
(A) It goes LOW at t = 0 and back HIGH at t = 3 ms.
(B) It goes LOW at t = 0.8 ms and back HIGH at t = 3 ms.
(C) It goes LOW at t = 0.8 ms and back HIGH at t = 1 ms.
(D) It goes HIGH at t = 0.8 ms and back LOW at t = 1 ms.
9. . Logical expression for NOR gate is:
(A) X = A̅̅̅.̅B̅
(B) X = A̅̅̅+̅̅̅B̅
(C) X = AB̅̅̅̅
(D) Both a and c
10. . A pulse is applied to each input of an exclusive-OR gate. One pulse goes HIGH at t = 0 and goes back LOW at t = 1 ms. The other pulse goes HIGH at t = 0.8 ms and goes back LOW at t = 3 ms. The output pulse can be described as follows:
(A) It goes HIGH at t = 0 and back LOW at t = 3 ms.
(B) It goes HIGH at t = 1 ms and back LOW at t = 3 ms.
(C) It goes HIGH at t = 0 and back LOW at t = 0.8 ms.
(D) both answers (b) and (c)
11. . Logical expression for exclusive OR gate is:
(A) X = A̅̅̅⨁̅̅̅̅B̅
(B) X = A̅̅̅+̅̅̅B̅
(C) X = AB̅̅̅̅
(D) X = A⨁ B
12. . Logical expression for exclusive NOR gate is:
(A) X = A̅̅̅⨁̅̅̅̅B̅
(B) X = A̅̅̅+̅̅̅B̅
(C) X = AB̅̅̅̅
(D) X = A⨁ B
13. . TTL stands for:
(A) Two Tables Logic
(B) Two Transistor Logic
(C) Transistor to Transistor Logic
(D) None of these